Description
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Designing a three-stage amplifier with Bipolar and CMOS transistors
Guanwu Li
TAMU
Nov 13, 2021
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Report
Introduction
A multistage amplifier is used in various electronic devices, they make use of the
basic principle blocks of amplifier design. They are mostly used in applications where high
gain; low output impedance and high output impedance are required. The downside of such
systems is that if they are not probably designed can end up using up a lot of power due to the
greater number of devices used. In this project, we are required to design a three-stage
amplifier using MOSFETs and BJTs. The design is required to meet certain specifications.
Objective
We are required to design an amplifier with;
|Av|≥ 25
Rin ≥ 200kΩ
3 dB Bandwidth > 200kHz
Harmonic distortion below -3dB
Vcc = 5V
Output large-signal voltage swing of 2V peak
Rload = 8 Ω
Procedure
Output Stage;
The output stage chosen was a class A output stage. It was chosen because it dissipates
less power and allows a full peak to peak swing. In the biasing of the output stage, the source
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voltage had to be chosen between 2.3-2.8V to allow a full swing of an output voltage with a
2V peak. The output stage is a simple Source follower circuit for better stability, the
transistor is biased using a resistor and a diode-connected transistor for better gain
transferability between the stages. This also makes use of an ac coupling capacitor to act as a
buffer to avoid load pulling or to disturb the biasing conditions of the amplifier. Smaller
capacitance is chosen to increase the bandwidth of the amplifier to meet the design
specifications
Second Stage
The second stage of the amplifier is just a repetition of the first stage but this time with
a much higher gain and source degeneration for better stability. From the parameters chosen
for the output stage, we work backward to obtain the bias conditions necessary to achieve the
specification. A common source configuration with source degeneration is used because it
provides a higher gain. The voltage required to form the drain is where we start our analysis
and solve backward to obtain the bias conditions and making sure the mos device remains in
saturation is important. The second stage is coupled with the first stage using ac coupling and
biased using a voltage divider circuit.
First Stage
The first stage of the amplifier is a simple common source single transistor amplifier
with source degeneration for stability. The circuit is biased using a voltage divider circuit and
the gate is ac coupled to the input signal. The first stage is biased to obtain a moderate gain
and also high impedance resistors are used to satisfy the design specifications.
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Figure 1 Schematic of circuit in Multisim
Simulation Results
Figure 2 DC Operating Point of each Stage
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Figure 3 AC sweep form 100Hz to 100kHz
Figure 4 Total Harmonic distortion of the output signal
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Figure 5 Fourier Analysis
Figure 6 Total power dissipated
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Checking for saturation(MOS)
M4( diode connected) , hence saturated
M4 in saturation
M2 and M3
VDS is greater than or equal to VGS – VTH
For VTH = 0.4, M2 and M3
Input Resistance
input of the first stage ( biopolar differential pair)
RIA= ( BETA(B) + 1) 2RE = 2RX
RIN = ( BETA(B) + 1) 2RE + 2RE is greater than or equal to 200k Ohms
RIN is greater than or equak to 200 because beta(B) > 50 and re is very large
RIN
Re= VI/IE
Re = 25mv/0.5mA
Re = 50ohms
Rid = 2( beta(B))(50 + 1K) = 212k Ohms
AV
AV1= -gM4(ro2//ro4)
AV2 = -gm2( R2//ro2)
AV3 = -gm3( R3//ro3//RL)
ID = 1/2UnCox(w/L)( VGS-VTH)2
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MOS transistor sizes{ Picking ensuring all MOS remain in saturation}
Transistor
W/L
M1
10/1
M2
20/1
UNCOX = 100A/V2
Gm2 = gm3 = √2(UnCOX(W/L)ID
ID2 = ID3 = 1/2UNCOXW/L( VGS – VTH)2
VGS = 1mV , VTH = 0.4mV
ID2 = ID3 = ½ x 10 x 20 ( 1 – 0.4)2
ID2 = 36mA
gm2 = gm3 = √(2(100) x 20 x 0.36m)
gm2 = gm3 = 12A/V
gm4 = √(2UnCoxw/L x ID )
ID4 = ½ x 100 x 40 x (1m – 0.4m)2
IDA = 72mA
gm4 = √(2 x 100 x 40 x 0.72)
gm4 = 2.4A/V
R2 = R3 = 5K ohms
Output machines
Let lambda be equal to a
RO2 = RO3 = 1/ aID
Picking reasonably , a = 0.1
Ro2 = ro3 = 1/ 0.1 x 0.26m = 28K ohms
Ro4 = 1/ 0.1 x 0.72 = 14K ohms
AV1 = 2.4 x ( 28K // 14K)
AV1 = -22.400
AV2 = -1.2 x ( 5K// 28K)
AV2 = -5090.9
AV3 = -1.2 x ( 5K // 28K// 8 ohms)
M3
20/1
M4
10/1
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AV3 = 0.958
OVERALL GAIN
AV = AV1 X AV2 X AV3
AV = 22.400 x 5090.9 x 0.958
= – 109.23
Gain is greater than or equal to 25
Observation
The gain of the dipolar differential pair is very high. Hence, the circuit has a high
gain. The supply voltage in theory can be reduced because the threshold voltage of the
devices used is 1.5V, which is only one-third of the supply being used, the only constraint
being the drain resistors used and the 8-ohm load we are supplying power to. The voltage
supply can be reduced by replacing the passive devices with active ones, like diodeconnected loads, and using current mirrors in the stages.
We can lower the supply voltage to about 3.5 V without affecting the mode of
operation of the transistors. Since we need to make sure that the drain voltage is always
greater than or equal to the gate voltage. On the edge of saturation, the gate voltage is equal
to the drain voltage and this is the minimum voltage we can have at the drain. There is also
some drop voltage drop across the drain resistor. We cannot reduce the drain resistor
drastically since the gain of our circuit is directly proportional to the gain of the system.
Hence, we are faced with another bottleneck. Hence with a supply of about 3.5V the device
can function normally.
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Design a three-stage amplifier with Bipolar and CMOS transistors to satisfy the following constraints. Note,
the design should use standard value resistors (no potentiometers),
• Av 25 (30%)
• Rin 200k12 (20%)
• 3 dB Bandwidth > 200kHz (10%)
Harmonic distortion below-30dB with Vimax = 5mVpk (10mVmp) measured at 10kHz input sine signal
(20%)
Vcc=5V (referred to a ground voltage of 0V)
Output large-signal voltage swing of 2V peak. (20%)
• Read = 82. Note, you may have to use multiple transistors in parallel in the output stage to drive
this load. Check the power ratings of the transistors.
• Use a minimum of 3 MOSFETs in your design. Note, if desired you can use more and also BJTS,
but the intent is that MOSFETs are a key part of your design.
Your report should describe the design procedure stage-by-stage, beginning with the output stage.
Can you lower Vec? Provide sufficient theoretical and quantitative justification on the Vcc choice.
Try to optimize Vcc on a per-stage basis to achieve the lowest power.
Both the preliminary and final report should include the following simulation results:
• DC operating points (voltages & currents) for each stage
• AC Plots from 100Hz to 100kHz: Av, Rin
• Transient plot of output signal with input 10kHz sine wave of 5mV amplitude
Frequency domain plot of above transient which shows the harmonic distortion. Note, to verify
the -30dB harmonic distortion spec, the harmonic distortion for a given harmonic is the ratio of the
harmonic power over the fundamental power.
Include the text output of the Fourier Analysis which states the Total Harmonic Distortion (THD).
Total power dissipation
The report should include the following measurement results:
• Bode plot showing the amplifier gain. Note, you may have to scale the plot to account for the input
voltage divider.
• Rin measurement
Transient plot of output signal with input 10kHz sine wave of 5mV amplitude
Frequency domain plot of above transient which shows the harmonic distortion.
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